This dissertation presents the analog harmonic transform (AHT) and a ﬁrst implementation in an integrated circuit. The transform is designed for a regular and simple hardware structure. It provides coeﬃcients relating to an input signal’s spectrum. These coeﬃcients also have a simple relationship to the signal’s Fourier series coeﬃcients. The AHT is deﬁned in its ideal form and evaluated for two example signal classiﬁcation applications. Both military vehicle and bearing fault classiﬁcation tasks are presented which validate the ability of a neural network to use the AHT coeﬃcients to correctly classify the input signals. Because any real use of the AHT for classiﬁcation would include various errors, a study determining the required hardware speciﬁcations is described.
These speciﬁcations are used to inform the design of a hardware implementation of the AHT coeﬃcient generation. A prototype system in a 0.13µm mixed-signal CMOS process was designed to conﬁrm the new system’s utility. The prototype chip included two separate blocks of AHT circuitry along with an on-board custom microprocessor to implement system control and supervision in a 4×4mm die area. A new digitally-controlled operational trans-conductance ampliﬁer (OTA) was designed as the core circuit element to support the AHT calculations. The OTA’s oﬀset and gain can be calibrated after fabrication to yield lower errors without signiﬁcant increases in chip area or power consumption. This enables hardware implementation of applications, such as the AHT, which have strict oﬀset requirements to maintain good system-level performance.
Testing of fabricated prototype chips conﬁrms the ability of digital oﬀset tuning to yield ampliﬁers having sub-10mV output-referred oﬀset with both low power and small die area. An algorithm was created to adaptively ﬁnd the optimum tuning code, needed because the tuning characteristic is not guaranteed monotonic. Testing also conﬁrms the reliable operation of OTAs with extremely large (giga ohm) output impedances. Low-frequency operation with long time constants requires these impedance levels to minimize integration capacitor size, the dominant factor in determining die area.
Figure 2.1 plots the two minimum processing energy curves from the above equations. It graphically illustrates the relationship between the two processing modes. High precision or large signal-to-noise ratio processing is most eﬃciently performed with digital techniques. Analog processing, however, retains a theoretical advantage at low SNRs, even in the limit of minimum digital energy usage of Etr = 8kT.This crossover occurs at an SNR of 28.2dB or a digital resolution of 4.1bit. Relative implementation eﬃciencies of real circuitry moves this boundary in either direction.
ANALOG HARMONIC TRANSFORM
For ground vehicles, the engine-related FF of the acoustic signal typically lies within the range 8Hz to 20Hz. The time-frequency responses of sample runs of the acquired acoustic signals from two tracked military vehicles passing by a sensor node are shown in Figure 3.4. The harmonic structure and the time-varying nature of the signals are apparent.
Figure 3.12 plots a contour map of average system-level classiﬁcation results for a range of gain/oﬀset standard deviations and noise levels. It is clear that gain variations with standard deviations up to 25% have little eﬀect on classiﬁcation performance. However, classiﬁcation rates are much more sensitive to oﬀset variations. Oﬀsets have the eﬀect of consistently over-estimating the signal energy at that harmonic, even if there is insigniﬁcant signal content at that particular frequency.
Figure 4.13 plots simulation results of the designed gain/oﬀset IDAC. The “pedestal” current provided by transistors M11 and M12 in Figure 4.11 was set to about 2nA, demonstrated in Figure 4.13 as the minimum, non-zero value of each of the two output currents.
ROM is present to assist in initializing the processor and RAM to a known state. The program counter is loaded with the ﬁrst ROM address location by design and code execution proceeds with the ROM contents. Code stored in the prototype chip’s ROM was able to initialize an externally-connected ﬂash chip via SPI port 0, copy its contents into the static RAM, and then jump to the ﬁrst RAM location. This feature allows programming the ﬂash chip by other means and also pre-ﬁlling the processor’s memory with custom code and data.
PROTOTYPE SYSTEM TESTING
The lower plot of Figure 5.10 records the integration time used for a given diﬀerential input while the upper plot shows the resulting output voltage at the end of the integration time.
Measured integrator output voltage for input frequencies in steps of 5Hz for a 10Hz basis function. Each plot’s horizontal axis is the relative starting phase between the basis function and input sinusoid over a complete cycle. Plots with blue circles indicate input frequencies where the results are expected to be non-zero. Higher frequencies for both the basis function and input reveal the presence of a dynamic error source caused by the non-symmetric single-ended integrator.
Simulation of a harmonic channel’s output after an integration period. The dynamic oﬀset is linearly dependent on both the input step size and the number of rise/fall transitions in a period (harmonic number). The basis function frequency was 5Hz with a 400ms integration time.
CONCLUSIONS AND FUTURE WORK
The analog harmonic transform presented in this dissertation is an alternative spectral feature extraction technique to traditional FFT or other transforms. It is speciﬁcally designed to have a simple, regular hardware implementation. The aspects of the AHT which set it apart from previous approaches are:
• Fourier series coeﬃcients may be calculated from the AHT coeﬃcients by simple back-substitution. Under the assumption of a band-limited input signal and precision computations, the calculated FS coeﬃcients are exact.
• Each quadrature set of AHT coeﬃcient calculations are mutually independent. This is in strong contrast to most eﬃcient digital transforms where all coefﬁcients must be calculated simultaneously. Because of this independence, all hardware associated with coeﬃcients which are not used in back-end processing may be powered oﬀ to save energy.
Broadly, future work can focus on two aspects: development of back-end algorithms and applications which use the AHT’s ability to extract only selected coeﬃcients, and improving the range of available ampliﬁer tuning techniques suited to use in AHT hardware.
Source: University of Nebraska-Lincoln
Author: Daniel J. White