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Low-Power Analog Processing

ABSTRACT

This dissertation presents the analog harmonic transform (AHT) and a first implementation in an integrated circuit. The transform is designed for a regular and simple hardware structure. It provides coefficients relating to an input signal’s spectrum. These coefficients also have a simple relationship to the signal’s Fourier series coefficients. The AHT is defined in its ideal form and evaluated for two example signal classification applications. Both military vehicle and bearing fault classification tasks are presented which validate the ability of a neural network to use the AHT coefficients to correctly classify the input signals. Because any real use of the AHT for classification would include various errors, a study determining the required hardware specifications is described.

These specifications are used to inform the design of a hardware implementation of the AHT coefficient generation. A prototype system in a 0.13µm mixed-signal CMOS process was designed to confirm the new system’s utility. The prototype chip included two separate blocks of AHT circuitry along with an on-board custom microprocessor to implement system control and supervision in a 4×4mm die area. A new digitally-controlled operational trans-conductance amplifier (OTA) was designed as the core circuit element to support the AHT calculations. The OTA’s offset and gain can be calibrated after fabrication to yield lower errors without significant increases in chip area or power consumption. This enables hardware implementation of applications, such as the AHT, which have strict offset requirements to maintain good system-level performance.

Testing of fabricated prototype chips confirms the ability of digital offset tuning to yield amplifiers having sub-10mV output-referred offset with both low power and small die area. An algorithm was created to adaptively find the optimum tuning code, needed because the tuning characteristic is not guaranteed monotonic. Testing also confirms the reliable operation of OTAs with extremely large (giga ohm) output impedances. Low-frequency operation with long time constants requires these impedance levels to minimize integration capacitor size, the dominant factor in determining die area.

LITERATURE REVIEW

Figure 2.1: Analog and digital minimum energy requirements

Figure 2.1: Analog and digital minimum energy requirements

Figure 2.1 plots the two minimum processing energy curves from the above equations. It graphically illustrates the relationship between the two processing modes. High precision or large signal-to-noise ratio processing is most efficiently performed with digital techniques. Analog processing, however, retains a theoretical advantage at low SNRs, even in the limit of minimum digital energy usage of Etr = 8kT.This crossover occurs at an SNR of 28.2dB or a digital resolution of 4.1bit. Relative implementation efficiencies of real circuitry moves this boundary in either direction.

ANALOG HARMONIC TRANSFORM

Figure 3.4: Time-Frequency acoustic response of two heavy-weight, tracked military vehicles

Figure 3.4: Time-Frequency acoustic response of two heavy-weight, tracked military vehicles

For ground vehicles, the engine-related FF of the acoustic signal typically lies within the range 8Hz to 20Hz. The time-frequency responses of sample runs of the acquired acoustic signals from two tracked military vehicles passing by a sensor node are shown in Figure 3.4. The harmonic structure and the time-varying nature of the signals are apparent.

Figure 3.12: Average classification rate variation over gain/offset standard deviation and added noise values

Figure 3.12: Average classification rate variation over gain/offset standard deviation and added noise values

Figure 3.12 plots a contour map of average system-level classification results for a range of gain/offset standard deviations and noise levels. It is clear that gain variations with standard deviations up to 25% have little effect on classification performance. However, classification rates are much more sensitive to offset variations. Offsets have the effect of consistently over-estimating the signal energy at that harmonic, even if there is insignificant signal content at that particular frequency.

HARDWARE DESIGN

Figure 4.13: IDAC outputs versus input code. Each of the 16 gain steps increase both currents while there are 256 steps for each gain value which skew the two output currents to tune the offset

Figure 4.13: IDAC outputs versus input code. Each of the 16 gain steps increase both currents while there are 256 steps for each gain value which skew the two output currents to tune the offset

Figure 4.13 plots simulation results of the designed gain/offset IDAC. The “pedestal” current provided by transistors M11 and M12 in Figure 4.11 was set to about 2nA, demonstrated in Figure 4.13 as the minimum, non-zero value of each of the two output currents.

Figure 4.17: Glitch-free clock switching for two inputs

Figure 4.17: Glitch-free clock switching for two inputs

ROM is present to assist in initializing the processor and RAM to a known state. The program counter is loaded with the first ROM address location by design and code execution proceeds with the ROM contents. Code stored in the prototype chip’s ROM was able to initialize an externally-connected flash chip via SPI port 0, copy its contents into the static RAM, and then jump to the first RAM location. This feature allows programming the flash chip by other means and also pre-filling the processor’s memory with custom code and data.

PROTOTYPE SYSTEM TESTING

Figure 5.10: Raw measured data from measuring the integrated output current versus differential input voltage

Figure 5.10: Raw measured data from measuring the integrated output current versus differential input voltage

The lower plot of Figure 5.10 records the integration time used for a given differential input while the upper plot shows the resulting output voltage at the end of the integration time.

Figure 5.23: Measured integrator output voltage for input frequencies

Figure 5.23: Measured integrator output voltage for input frequencies

Measured integrator output voltage for input frequencies in steps of 5Hz for a 10Hz basis function. Each plot’s horizontal axis is the relative starting phase between the basis function and input sinusoid over a complete cycle. Plots with blue circles indicate input frequencies where the results are expected to be non-zero. Higher frequencies for both the basis function and input reveal the presence of a dynamic error source caused by the non-symmetric single-ended integrator.

Figure 5.25: Simulation of a harmonic channel’s output after an integration

Figure 5.25: Simulation of a harmonic channel’s output after an integration

Simulation of a harmonic channel’s output after an integration period. The dynamic offset is linearly dependent on both the input step size and the number of rise/fall transitions in a period (harmonic number). The basis function frequency was 5Hz with a 400ms integration time.

CONCLUSIONS AND FUTURE WORK

Conclusions

The analog harmonic transform presented in this dissertation is an alternative spectral feature extraction technique to traditional FFT or other transforms. It is specifically designed to have a simple, regular hardware implementation. The aspects of the AHT which set it apart from previous approaches are:
• Fourier series coefficients may be calculated from the AHT coefficients by simple back-substitution. Under the assumption of a band-limited input signal and precision computations, the calculated FS coefficients are exact.
• Each quadrature set of AHT coefficient calculations are mutually independent. This is in strong contrast to most efficient digital transforms where all coefficients must be calculated simultaneously. Because of this independence, all hardware associated with coefficients which are not used in back-end processing may be powered off to save energy.

Future Work

Broadly, future work can focus on two aspects: development of back-end algorithms and applications which use the AHT’s ability to extract only selected coefficients, and improving the range of available amplifier tuning techniques suited to use in AHT hardware.

Source: University of Nebraska-Lincoln
Author: Daniel J. White

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